Register file generator

As the ASIC/IP designer, coding of the register files can greatly simplify using an automated flow. It is also one of the efficient way to manage data consistently across several phases of design.

Automation example:

Frame maker/ word document of register description --> XML format -->
Perl XML parser --> generate targets ( VHDL/verilog code, HTML documents, C structure definitions and access methods for Firmware coding, system verilog/specman 'e' targets for verification)