Modeling delays in verilog

Verilog supports three kinds of delay modeling

• Distributed delay modelling - As the name indicates the module delay is consists of delays from the sub components.

          Verilog code example:

           module AND_OR (Y, A, B, C, D);
              output Y;
              input A, B, C, D;
              and #1.0 I0(outA, A, B);
              //  #(1.0:1.1:1.2, 0.9:1.0:1.1) min:typ:max triplets for rise, fall delays
              nor #2.0 I1(Y, C, D, outA);
           endmodule;

Total delay from the above example is 3 time units for output Y from pin A, B. Delays can be more precisely specified using min:typ:max triplets and sets for rise, fall delays. For digital RTL simulations, the simulators can take these delays into account when above module is compiled with +delay_mode_distributed simulator option or using a dummy verilog module (first module in the compile order) with `delay_mode_distributed verilog directive.

• Lumped delay - difference between the distributed delay mode and the lumped delay is that only the sub component at the output of the module represents the total delay 

       module AND_OR (Y, A, B, C);
              output Y;
              input A, B, C;              and I0(outA, A, B);
              or #3.0 I1(Y, C, outA);

      endmodule; 

Same verilog directive/simulator compile switch as delay mode distributed are used for this case.

• Pin-to-Pin/path delays - This approach treats the insides of the module as the black box and uses the ports to specify the delay from different input/inouts to output/inout ports. Verilog has special construct 'specify' to use for the path delay modeling. SDF can be used for back annotating the delays if the SDF constructs are matched with the timing model described in the specify. This allows the back annotated simulation of the post layout netlist

 module AND_OR (Y, A, B, C);
              output Y;
              input A, B, C;               and I0(outA, A, B);
              or I1(Y, C, outA);

  specify
    // delay parameters
    specparam
      tplhAY = 1.0,
      tphlAY = 1.0,
      tplhBY = 1.0,
      tphlBY = 1.0,
      tplhCY = 1.0,
      tphlCY = 1.0;

    // path delays ( using conditional delays for C to Y)
      (A *> Y) = (tplhAY, tphlAY);
      (B *> Y) = (tplhBY, tphlBY);
    if (A == 1'b1 && B == 1'b0 )
       (C *> Y) = (tplhCY, tphlCY);
    if (A == 1'b0 && B == 1'b1 )
       (C *> Y) = (tplhCY, tphlCY);
    if (A == 1'b0 && B == 1'b0 )
       (C *> Y) = (tplhCY, tphlCY);

  endspecify

endmodule;

 Example SDF construct

(CELL
  (CELLTYPE "AND_OR")
  (INSTANCE top_tb/DUT/i_a/i_b)
  (DELAY
    (ABSOLUTE
    (IOPATH A Y (0.09168:0.09168:0.09168) (0.10759:0.10759:0.10759))
    (IOPATH B Y (0.10432:0.10432:0.10432) (0.15321:0.15321:0.15321))
    (COND A == 1'b1 && B == 1'b0 (IOPATH C Y (0.04601:0.04601:0.04601) (0.05479:0.05479:0.05479)))
    (COND A == 1'b0 && B == 1'b1 (IOPATH C Y (0.04602:0.04602:0.04602) (0.05478:0.05478:0.05478)))
    (COND A == 1'b0 && B == 1'b0 (IOPATH C Y (0.04610:0.04610:0.04610) (0.05423:0.05423:0.05423)))
    )
  )
)