Asynchronous FIFO depth

Elastic FIFO/Asynchronous FIFO's are used to compensate for any frequency drift between the two clock domains. Although the system design has to ensure by protocol to compensate for long-term wander, these Elastic FIFO's are needed to handle the wander between the compensation periods. For instance PCIe protocol requires the SKIP ordered sets to be transmitted at regular internals to compensate for the clock frequency drift. Similarly SGMII, 1000BASE-X uses the IDLE order sets to compensate.

Example of the elastic buffer depth calculation:
Assume protocol specifies 600ppm frequency difference is allowed.
frequency difference = 600/1e6 = .0006
1 UI slip occurs every 1/.0006 = 1666.66 bits
Assume the maximum packet length (in bytes) transmitted before the compensation start  = 5660 bytes
packet size (in bits) = 5660 * 8 = 45280 bits
total number of bits slips = 45280/1666.66 = 28 bits (rounded to ceil) = 4 bytes (rounded to ceil)

Thus the elastic buffer depth of +/-4 ( 8) required  to compensate for the read, write pointers drift. However it is good practice to have additional depth to overcome the boundary conditions.