Having experienced with several design phases of the PCIe - Physical Layer design, integrating the controllers and PHY's together in SOC platforms, bringing up in Lab, characterizing in high speed lab, I attempt to share some of my knowledge in this post
PCIe Throughput calculation
Taking example of PCIe Gen1. Maximum physical link bandwidth is 2.5Gbps. Because it is encoded with 8b10b scheme, effective throughput is 2.0Gbps.
Assuming a typical trade off for the band width utilization and the retry buffer size, ACK/NACK and flow control updates are scheduled to minimize the negative impact of retry.
for e.g. Case 1 : with 128 bytes payload size data, the TLP size will be 128 bytes (data) + header (12-16 bytes) + ECRC (4 bytes) + Sequence number (2 bytes) + LCRC (4 bytes) + STP (1 byte) + END(1byte) = 152 bytes (18.75% overhead); in other words we can only use 81.53% of the link effective bandwidth (2Gbps), which is 1.63Gbps.
Now considering the other overhead on the link for the transmission of the Flow control and the ACK/NACK and SKIP order sets.
for instance with 1ACK + 1FC per 4 data packets128 bytes payload data causes to use additional 8 bytes (FC DLLP) and 8 bytes (ACK DLLP) which is another 3% overhead, implies the effective bandwidth is 0.97*1.63 = 1.58Gbps.
